onerr {resume}
add list -bin /test_bench/clk
add list -hex /test_bench/DUT/the_JTAG/av_address
add list -bin /test_bench/DUT/the_JTAG/av_chipselect
add list -bin /test_bench/DUT/the_JTAG/av_irq
add list -bin /test_bench/DUT/the_JTAG/av_read_n
add list -hex /test_bench/DUT/the_JTAG/av_readdata
add list -bin /test_bench/DUT/the_JTAG/av_waitrequest
add list -bin /test_bench/DUT/the_JTAG/av_write_n
add list -hex /test_bench/DUT/the_JTAG/av_writedata
add list -bin /test_bench/DUT/the_JTAG/dataavailable
add list -bin /test_bench/DUT/the_JTAG/readyfordata
add list -hex /test_bench/DUT/the_SDRAM/az_addr
add list -hex /test_bench/DUT/the_SDRAM/az_be_n
add list -bin /test_bench/DUT/the_SDRAM/az_cs
add list -hex /test_bench/DUT/the_SDRAM/az_data
add list -bin /test_bench/DUT/the_SDRAM/az_rd_n
add list -bin /test_bench/DUT/the_SDRAM/az_wr_n
add list -bin /test_bench/DUT/the_SDRAM/clk
add list -hex /test_bench/DUT/the_SDRAM/za_data
add list -bin /test_bench/DUT/the_SDRAM/za_valid
add list -bin /test_bench/DUT/the_SDRAM/za_waitrequest
add list -asc /test_bench/DUT/the_SDRAM/CODE
add list -hex /test_bench/DUT/the_SDRAM/zs_addr
add list -hex /test_bench/DUT/the_SDRAM/zs_ba
add list -hex /test_bench/DUT/the_SDRAM/zs_cs_n
add list -bin /test_bench/DUT/the_SDRAM/zs_ras_n
add list -bin /test_bench/DUT/the_SDRAM/zs_cas_n
add list -bin /test_bench/DUT/the_SDRAM/zs_we_n
add list -hex /test_bench/DUT/the_SDRAM/zs_dq
add list -hex /test_bench/DUT/the_SDRAM/zs_dqm
add list -hex /test_bench/DUT/the_CPU/i_readdata
add list -hex /test_bench/DUT/the_CPU/i_readdatavalid
add list -hex /test_bench/DUT/the_CPU/i_waitrequest
add list -hex /test_bench/DUT/the_CPU/i_address
add list -hex /test_bench/DUT/the_CPU/i_read
add list -hex /test_bench/DUT/the_CPU/clk
add list -hex /test_bench/DUT/the_CPU/reset_n
add list -hex /test_bench/DUT/the_CPU/d_readdata
add list -hex /test_bench/DUT/the_CPU/d_waitrequest
add list -hex /test_bench/DUT/the_CPU/d_irq
add list -hex /test_bench/DUT/the_CPU/d_address
add list -hex /test_bench/DUT/the_CPU/d_byteenable
add list -hex /test_bench/DUT/the_CPU/d_read
add list -hex /test_bench/DUT/the_CPU/d_write
add list -hex /test_bench/DUT/the_CPU/d_writedata
add list -hex /test_bench/DUT/the_CPU/the_CPU_test_bench/W_pcb
add list -asc /test_bench/DUT/the_CPU/the_CPU_test_bench/W_vinst
add list -hex /test_bench/DUT/the_CPU/the_CPU_test_bench/W_valid
add list -hex /test_bench/DUT/the_CPU/the_CPU_test_bench/W_iw
add list -bin /test_bench/DUT/the_IRDA/chipselect
add list -hex /test_bench/DUT/the_IRDA/address
add list -hex /test_bench/DUT/the_IRDA/writedata
add list -hex /test_bench/DUT/the_IRDA/readdata
add list -bin /test_bench/DUT/the_IRDA/tx_ready
add list -asc /test_bench/DUT/the_IRDA/tx_data
add list -bin /test_bench/DUT/the_IRDA/rx_char_ready
add list -asc /test_bench/DUT/the_IRDA/rx_data
configure list -usestrobe 0
configure list -strobestart {0 ps} -strobeperiod {0 ps}
configure list -delta none
configure list -usegating 1
configure list -gateexpr { /test_bench/clk'rising }